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　　WHEN THE FAIRNESS ALGORITHM IS DISABLED, DMA ACCESS IS GRANTED
　　BASED SOLELY ON THE PRIORITY LEVEL; NO BUS BANDWIDTH GUARANTEES
　　ARE MADE.
　　4.4.4 TRANSACTION MODES SUPPORTED
　　THE FLEXIBLE CONFIGURATION OF EACH DMA CHANNEL AND THE ABILITY TO
　　CHAIN MULTIPLE CHANNELS ALLOW THE CREATION OF BOTH SIMPLE AND
　　COMPLEX USE CASES. GENERAL USE CASES INCLUDE, BUT ARE NOT
　　LIMITED TO:
　　4.4.4.1 SIMPLE DMA
　　IN A SIMPLE DMA CASE, A SINGLE TD TRANSFERS DATA BETWEEN A
　　SOURCE AND SINK (PERIPHERALS OR MEMORY LOCATION).
　　4.4.4.2 AUTO REPEAT DMA
　　AUTO REPEAT DMA IS TYPICALLY USED WHEN A STATIC PATTERN IS REPETITIVELY
　　READ FROM SYSTEM MEMORY AND WRITTEN TO A PERIPHERAL. THIS
　　IS DONE WITH A SINGLE TD THAT CHAINS TO ITSELF.
　　4.4.4.3 PING PONG DMA
　　A PING PONG DMA CASE USES DOUBLE BUFFERING TO ALLOW ONE BUFFER
　　TO BE FILLED BY ONE CLIENT WHILE ANOTHER CLIENT IS CONSUMING THE
　　DATA PREVIOUSLY RECEIVED IN THE OTHER BUFFER. IN ITS SIMPLEST FORM,
　　THIS IS DONE BY CHAINING TWO TDS TOGETHER SO THAT EACH TD CALLS
　　THE OPPOSITE TD WHEN COMPLETE.
　　4.4.4.4 CIRCULAR DMA
　　CIRCULAR DMA IS SIMILAR TO PING PONG DMA EXCEPT IT CONTAINS MORE
　　THAN TWO BUFFERS. IN THIS CASE THERE ARE MULTIPLE TDS; AFTER THE LAST
　　TD IS COMPLETE IT CHAINS BACK TO THE FIRST TD.
　　4.4.4.5 SCATTER GATHER DMA
　　IN THE CASE OF SCATTER GATHER DMA, THERE ARE MULTIPLE NONCONTIGUOUS
　　SOURCES OR DESTINATIONS THAT ARE REQUIRED TO EFFECTIVELY
　　CARRY OUT AN OVERALL DMA TRANSACTION. FOR EXAMPLE, A PACKET MAY
　　NEED TO BE TRANSMITTED OFF OF THE DEVICE AND THE PACKET ELEMENTS,
　　INCLUDING THE HEADER, PAYLOAD, AND TRAILER, EXIST IN VARIOUS
　　NONCONTIGUOUS LOCATIONS IN MEMORY. SCATTER GATHER DMA ALLOWS
　　THE SEGMENTS TO BE CONCATENATED TOGETHER BY USING MULTIPLE TDS
　　IN A CHAIN. THE CHAIN GATHERS THE DATA FROM THE MULTIPLE LOCATIONS.
　　A SIMILAR CONCEPT APPLIES FOR THE RECEPTION OF DATA ONTO THE
　　DEVICE. CERTAIN PARTS OF THE RECEIVED DATA MAY NEED TO BE
　　SCATTERED TO VARIOUS LOCATIONS IN MEMORY FOR SOFTWARE PROCESSING
　　CONVENIENCE. EACH TD IN THE CHAIN SPECIFIES THE LOCATION FOR
　　EACH DISCRETE ELEMENT IN THE CHAIN.
　　4.4.4.6 PACKET QUEUING DMA
　　PACKET QUEUING DMA IS SIMILAR TO SCATTER GATHER DMA BUT SPECIFICALLY
　　REFERS TO PACKET PROTOCOLS. WITH THESE PROTOCOLS, THERE MAY
　　BE SEPARATE CONFIGURATION, DATA, AND STATUS PHASES ASSOCIATED
　　WITH SENDING OR RECEIVING A PACKET.
　　FOR INSTANCE, TO TRANSMIT A PACKET, A MEMORY MAPPED CONFIGURATION
　　REGISTER CAN BE WRITTEN INSIDE A PERIPHERAL, SPECIFYING THE
　　OVERALL LENGTH OF THE ENSUING DATA PHASE. THE CPU CAN SET UP
　　THIS CONFIGURATION INFORMATION ANYWHERE IN SYSTEM MEMORY AND
　　COPY IT WITH A SIMPLE TD TO THE PERIPHERAL. AFTER THE CONFIGURATION
　　PHASE, A DATA PHASE TD (OR A SERIES OF DATA PHASE TDS) CAN
　　BEGIN (POTENTIALLY USING SCATTER GATHER). WHEN THE DATA PHASE
　　TD(S) FINISH, A STATUS PHASE TD CAN BE INVOKED THAT READS SOME
　　MEMORY MAPPED STATUS INFORMATION FROM THE PERIPHERAL AND
　　COPIES IT TO A LOCATION IN SYSTEM MEMORY SPECIFIED BY THE CPU
　　FOR LATER INSPECTION. MULTIPLE SETS OF CONFIGURATION, DATA, AND
　　STATUS PHASE “SUBCHAINS” CAN BE STRUNG TOGETHER TO CREATE LARGER
　　CHAINS THAT TRANSMIT MULTIPLE PACKETS IN THIS WAY. A SIMILAR
　　CONCEPT EXISTS IN THE OPPOSITE DIRECTION TO RECEIVE THE PACKETS.